Methods and apparatus for bridged data transmission and protocol translation in a high-speed serialized data system

ABSTRACT

An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.

FIELD OF THE INVENTION

The present invention relates broadly to devices connected to ahigh-speed serial bus. Specifically, the present invention relates tobridging data transmission between IEEE 1394-compliant devices andEthernet-compliant devices.

BACKGROUND

A “bus” is a collection of signals interconnecting two or moreelectrical devices that permits one device to transmit information toone or more other devices. There are many different types of buses usedin computers and computer-related products. Examples include thePeripheral Component Interconnect (“PCI”) bus, the Industry StandardArchitecture (“ISA”) bus and the Universal Serial Bus (“USB”), to name afew. Bus operation is usually defined by a standard that specifiesvarious concerns such as the electrical characteristics of the bus, howdata is to be transmitted over the bus, how requests for data areacknowledged, and the like. Using a bus to perform an activity, such astransmitting data, requesting data, etc., is generally called running a“cycle.”Standardizing a bus protocol helps to ensure effectivecommunication between devices connected to the bus, even if such devicesare made by different manufacturers. Any company wishing to make andsell a device to be used on a particular bus, provides that device withan interface unique to the bus to which the device will connect.Designing a device to particular bus standard ensures that device willbe able to communicate properly with all other devices connected to thesame bus, even if such other devices are made by differentmanufacturers.

Thus, for example, an internal fax/modem (i.e., internal to a personalcomputer) designed for operation on a PCI bus will be able to transmitand receive data to and from other devices on the PCI bus, even if eachdevice on the PCI bus is made by a different manufacturer.

Problems occur when devices located on buses or networks using differentlow-level protocols are made to communicate with each other. One exampleinvolves two very popular standards, the IEEE 1394 family of serial busprotocols, and the IEEE 802.3 family of Ethernet network protocols.Despite the fact that there are versions of both protocols that use thesame cables and connectors, and both support the higher level “InternetProtocol” (IP), devices implementing the Ethernet-compliant networkinterface are unable to communicate with devices implementing the1394-compliant bus interface because of the differences existing betweenthe respective protocols. Because of the large number of existingdevices that use one protocol or the other, this communication gap islikely to widen as standards are developed in the two protocols. Thus,there is a heartfelt need for a solution that bridges the communicationgap between protocols and effectively allows devices to communicate witheach other across different bus or networking architectures.

SUMMARY

The present invention solves the problems discussed above by providing amethod and apparatus for communicating data between a gigabit Ethernetarchitecture and a IEEE 1394-compliant architecture. In an embodiment,the present invention provides a hub device that incorporates a1394-compliant physical layer and an Ethernet physical layer and bridgescommunication between the two architectures at the Internet Protocollayer.

In another embodiment, the present invention provides a method ofcommunicating data between an Ethernet system and a 1394-compliantsystem by transmitting an S800 1394b stream within a 1000 BASE-Ttransmit stream by inserting an illegal 1394b symbol into the streamapproximately once for every 59 regular symbols transmitted in the 1000BASE-T transmit stream. This illegal symbol is inserted to compensatefor the fact that the bit rate for S800 after an 8B10B encode is 983.04Mbps+/−100 ppm, and the bit rate for 1000 BASE_T stream is slightlyfaster at 1000 Mbps+/−50 ppm. The illegal symbol can be inserted intothe transmit stream at a fixed rate, or in another embodiment, byutilizing a one-symbol queue that is fed by a 1394b transmitting portand drained by logic which supplies it to the 1000 base Tx PHY. In thisembodiment, when the queue underflows, the illegal symbol is generatedby the logic with drains the queue. To receive a 1394-compliant streamover an Ethernet bus, the same approach can be followed, The illegalsymbols received are recognized and ignored. In an embodiment, a receiveFIFO is centered when the start of a packet, is recognized, i.e. enoughsymbols are buffered to allow for the jitter in the arrival rateresulting from deleting the illegal symbols, and also to compensate forppm clock differences which might result in symbols being placed in theFIFO at a slower rate than they are removed.

In another aspect of the present invention, an autonegotiation processexecutes to select either an Ethernet protocol or a 1394b protocol to beused on a connected communication medium. In this manner, data from agigabit Ethernet architecture, or data from a1394-compliantarchitecture, can be transmitted across a common medium, without anymanual configuration required of a user. In this embodiment, fiveregisters are included on a 1394b PHY, but the port in the 1394b PHYruns off the same 125 MHz clock as is provided by the gigabit mediaindependent interface (GMII). A modulo 5 counter is included on the1394b PHY to control symbol insertion into the transmit queue located onthe 1394b side. The modulo 5 counter iteratively counts from 0 to 4. Ifthe modulo 5 counter has a zero value, then the 1394b side does not pusha 10-bit number into the FIFO. For cases where the counter has anon-zero value, the 1394b side pushes the 10-bit symbol assembled topreserve clock consistency across different clock domains.

In yet another aspect, the present invention provides a method oftransmitting data across a high-speed serial bus. In accordance with anIEEE 1394-compliant PHY's TX symbol clock, a 10-bit symbol is generatedon an IEEE 1394-compliant PHY. The 10-bit symbol is scrambled andencoded and placed in a FIFO. In accordance with an IEEE 802.3-compliantPHY's TX clock, the 10-bit symbol is removed from the FIFO, an 8-bitbyte is derived from the removed 10-bit symbol; and sent to an IEEE802.3-compliant PHY. A symbol is removed from the FIFO on four out ofevery five GMII TX clock cycles. A null 10-bit symbol is placed in theFIFO if there are no 10-bit symbols present in the FIFO. The modulo 5counter is used to derive the 8-bit byte in the following manner: First,the 8-bit byte is derived from the 10-bit symbol by using 8 bits fromthe extracted 10-bit symbol, and the two remaining bits are stored. Thenext 8-bit byte is derived by extracting from the FIFO a second 10-bitsymbol and assembling an 8-bit byte from the stored two bits and sixbits from the extracted second 10-bit symbol, the four remaining bitsfrom the extracted second symbol are stored and the second 8-bit byte issent to the IEEE 802.3-compliant PHY. A third 8-bit byte is derived byextracting from the FIFO a third 10-bit symbol and assembling an 8-bitbyte from the four stored bits and four bits from the third extractedsymbol. The six remaining bits from the extracted third symbol arestored and the third 8-bit byte is sent to the IEEE 802.3-compliant PHY.A fourth 8-bit byte is derived by extracting from the FIFO a fourth10-bit symbol, and assembling an 8-bit byte from the six stored bits and2 bits from the extracted fourth 10-bit symbol. The eight remaining bitsfrom the extracted fourth symbol are stored and the fourth 8-bit byte issent to the IEEE 802.3-compliant PHY. A fifth 8-bit byte is derived fromthe stored eight remaining bits and sent to the IEEE 802.3-compliantPHY.

On the receiving side, the method comprises receiving an 8-bit byte, andin accordance with a GMII RX clock, if the received 8-bit byte containsa null symbol, then deleting the null symbol; else storing the 8-bitbyte in a first register; receiving a second 8-bit byte that does notcontain a null symbol and storing it in a second register. A 10-bitsymbol is assembled from the 8-bit byte stored in the first register andappending two bits from the 8-bit byte stored in the second register.The assembled 10-bit symbol is placed in a first FIFO. In accordancewith a second clock, the 10-bit symbol is removed from the first FIFO.8B10B and control decoding is performed on it before it is placed in asecond FIFO. In accordance with a third clock, the decoded 10-bit symbolis removed from the second FIFO; and sent to an IEEE 1394-compliant PHY.The frequency of null character deletion is used to control a phasedlocked loop associated with the second clock.

In still another aspect, the present invention provides a method oftransmitting data across a high-speed serial bus, comprising: inaccordance with a first TX symbol clock: generating a 10-bit symbol onan IEEE 1394-compliant PHY having a port interface, placing thegenerated 10-bit symbol on the port interface, performing flaggedencoding the 10-bit symbol, and placing the 10-bit symbol in a FIFO. Inaccordance with a second TX clock, the 10-bit symbol is removed from theFIFO, an 8-bit byte is derived from the removed 10-bit symbol; and sentto an IEEE 802.3-compliant PHY.

In yet another aspect, the present invention provides an apparatus fortransmitting data across a high-speed serial bus, the method comprising:an IEEE 802.3-compliant PHY having a GMII interface; an IEEE1394-compliant PHY in communication with the IEEE 802.3-compliant PHY; afirst connection, the first connection for transmitting data between adevice and the IEEE 802.3-compliant PHY; and a second connection, thesecond connection for transmitting data between a device and the IEEE1394-compliant PHY. The IEEE 1394-compliant PHY is in communication withthe IEEE 802.3-compliant PHY via a switch. The switch determines whetherdata transmission is be routed to the IEEE 802.3-compliant PHY or theIEEE 1394-compliant PHY. An autonegotiation mechanism determines whetherdata is to be routed between the IEEE 802.3-compliant PHY and the IEEE1394-compliant PHY, or whether data is to be routed through the IEEE802.3-compliant PHY to the first connection.

Other features and advantages of the present invention will becomeapparent from reading the following detailed description, whenconsidered in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates in block diagram form structural and functionelements in an embodiment;

FIG. 2 illustrates functional components included in a port inaccordance with an embodiment of the present invention;

FIG. 3 illustrates in data flow diagram form translation between 8-bitbytes and 10-bit symbols in accordance with an embodiment of the presentinvention;

FIG. 4 illustrates the relationship between 10-bit symbols and 8-bitcharacters;

FIG. 5 illustrates functional components in an alternative embodiment ofa port in accordance with the present invention;

FIG. 6 illustrates in data flow diagram form an embodiment of thepresent invention that uses 802.3 clause 40 idle bytes instead ofillegal symbols to perform translation between 10-bit symbols and 8-bitcharacters but does so without having to recover an RX receive clock;and

FIG. 7 illustrates in data flow diagram form an embodiment of thepresent invention that uses 802.3 clause 40 idle bytes instead ofillegal symbols to perform translation between 10-bit symbols and 8-bitcharacters but does so without having to recover a TX symbol clock.

SUMMARY OF THE INVENTION

Various embodiments of the present invention utilize a 1000 BASE-T PHYthat transmits and receives at no less than 0.9999 gbit/sec, and a 1394bPHY having a cable interface that utilizes a bit stream rate of no morethan 0.98304+100 ppm=0.9831383 gbit/sec. Thus, the fastest S800 1394btransmission rate can be accommodated by the slowest 1000 BASE-T stream.

In an embodiment, the present invention upshifts an S800 1394b stream byinserting an illegal symbol within the transmit stream approximatelyonce for every 59 regular symbols. In an embodiment, the illegal symbolis either all ones or all zeros since those are the furthest Hammingdistance from 1394b control symbols or data symbols. In variousembodiments, insertion of this illegal symbol can be performed at afixed rate, or by utilizing a one-symbol FIFO that is fed by the 1394btransmitting port and drained by the 1000 base TX PHY. In thisembodiment, when the FIFO underflows, the extra symbol is generated. Onreceive, the same approach can be followed. In an embodiment, a FIFO iscentered at the start of a packet.

In another embodiment of the present invention, the 1000 base-T transmitstream requires a number of Ethernet IDLE symbols to appearperiodically. A small transmit FIFO is provided and, when it underflows,transmission of the 1394b symbols is halted and the 1000 base TX PHY isinstructed to transmit Ethernet IDLE symbols for 11 Ethernet symboltimes. During this time, the transmit FIFO is filling. After the 11Ethernet symbol times has passed, transmission of 1394b symbols isresumed. Insertion of these idle symbols satisfies a requirement for1000 base T transmission.

Directing attention to FIG. 1, a functional representation of anembodiment of the present invention is provided. The functional elementsillustrated in FIG. 1 can be incorporated into a node device thatcommunicates over a serial bus as described above to allow a user toimplement a variety of Internet-based functions over a 1394-compliantbus architecture. Integrated PHY chip 100 includes 802.3 clause 40 PHY102 having external connection 103 and GMII interface 104, andintegrated 1394 PHY 106, having at least one external connector 107,controllably connected to 802.3 Clause 40 PHY 102. 1394 PHY 106 includesat least one 1394 port 108, each having a FIFO 110 for delivering bits,characters, or symbols to 1394 arbitration and data repeat module 112.Also included in 1394 PHY 106 is port 114, which also communicates bits,characters or symbols to 1394 arbitration and data repeat module 112 viaFIFO 116. In an embodiment, FIFO 116 is sized larger than FIFO 110 toaccommodate additional latencies experienced on port 114. Port 114 alsoconnects to 802.3 Clause 40 PHY 102 via a switch 118. In an embodiment,switch 118 is controllably set between port 114 and GMII interface 104according to an autonegotiation process described herein. 1394arbitration and data repeat module 112 performs bus arbitration as wellas routing data received between link layer interface 122 and/or ports108, 114. Arbitration is handled by module 112 to determine whether PHY106 is to transmit over a connected serial bus or receive data over theserial bus. Link layer 124 assembles a stream of symbols received overlink layer interface 122 into packets that are transmitted forward overprotocol layer 126. Conversely, link layer 124 translates packetsreceived from protocol layer 126 into a stream of symbols that can bepassed to the link layer interface 122. In an embodiment, link layer 124and protocol layer 126 are implemented on a shared chip 128. IP 1394firmware module 130 includes logic for implementing application-specificprotocols that transport Internet protocol (IP)-format packets over 1394hardware and logic. IP bridge firmware module 132 bridges packetstransmitted between IP bridge firmware module 132 and implements aseparate IP subnet or an 802.3 subnet and bridges communication betweenthese two types of subnets according to IP standards. Alternatively, IPbridge firmware module 132 manages a common subnet between 802.3 Clause40 PHY 102 and 1394 PHY 106 and ensures that IP addressing oftransmitted packets is distinct. The GMII side of the present inventionincludes 802.3 IP firmware module 134, that performs similar functionsfor 802.3 Claude 40 PHY 102 as IP 1394 firmware module 130 provides for1394 PHY 106, and chip 138, containing GMII side 802.3 protocol layermodule 140 and 802.3 media access card (MAC) 142, which perform similarfunctions for the GMII side as 1392 protocol layer 126 and 1394 linklayer module 124 perform for the 1394 side, respectively.

Directing attention to FIG. 2, port 114 can be conceptualized has havinga 1394 arbitration side of functionality and a GMII side offunctionality. In an embodiment, FIFO 200 is included on port 114, andin combination with register 202 and register 204, and modulo 5 counter206 is used to extract 10-bit symbols from the 1394 side of port 114 andprocess portions of the extracted symbols into 8-bit characters to betransmitted to GMII interface 104, thus bridging communication between a1394-compliant system and a gigabit Ethernet systems. In an embodiment,registers 208 and 210 are provided for assembly of 10-bit symbols from8-bit characters arriving from GMII interface 104 over connection 120.However, in another embodiment, these 10-bit symbols can be assembledusing registers 202 and 204.

Directing attention to FIG. 3, autonegotiation selects whether anEthernet or a protocol from the 1394 family of protocols is to be usedon the connection thus determining the selection made by switch 118. Inthis embodiment, the 1394 side runs off the same 125 MHz clock as isprovided by GMII interface 104. The 1394 side of port 114 generates10-bit symbols using a 98.304 MHz clock and pushes them into FIFO 200using this clock. At the other end of FIFO 200, TX Adaptation module 220extracts the 10-bit symbols from FIFO 200 using the GMII 125 MHz clockand modulo 5 counter 206. Modulo 5 counter 206 supplies values rangingfrom 0 to 4. If the modulo 5 counter reads 0, then a 10-bit symbol isextracted, but only eight bits of it are used. In an embodiment, theassembled 8-bit character can be retained in register 204 untiltransmitted to GMII interface 104. The remaining two bits are retainedin register 202 for use on the next GMII clock signal. If modulo 5counter 206 reads 1, then a 10-bit symbol is extracted, but only sixbits of it are used and what is transmitted combines the two bits storedin register 202 plus these six extracted bits. This results in four bitsbeing left over, which are stored in register 202. If modulo 5 counter206 reads 2, then the four left-over bits from register 202 are combinedwith four bits from the next 10-bit symbol that is extracted from FIFO200, resulting in six bits being left over from the extracted 10-bitsymbol. These remaining six bits are retained in register 202. If modulo5 counter 206 reads 3, then the six bits in register 202 are combinedwith two bits from the next extracted symbol, and the remaining eightbits are stored in register 202. If modulo 5 counter 206 reads 4, thenno new symbol is extracted, and the eight left over bits are sent overGMII interface 104. If modulo 5 counter 206 has a zero value, then the1394 side of port 114 does not push a 10-bit number into FIFO 200. PHY102 ensures that the GMII RX clock is locked to the GMII TX clock. If nosymbol is available in FIFO 200, TX Adaptation module 220 inserts anillegal or null 10-bit symbol into FIFO 200.

For translation of data in the opposite direction, where 10-bit symbolsare formed from 8-bit characters, synchronization characters (i.e.illegal characters) force the value of modulo 5 counter 206 to zero andhold it there. The first valid 8-bit character that is received viaconnection 120 is copied into register 208 with the counter value stillat zero, so the 1394 side of port 114 takes no action. The next 8-bitcharacter received over connection 120 is placed in register 210. The1394 side of port 114 assembles a 10-bit symbol by taking the eight bitsfrom register 208, appending two bits from register 210, and treatingthe resulting 10-bit symbol as if it had been received on 1394b port108. Most such symbols are pushed into the bport RX FIFO, while others,such as repeated request or control symbols, and illegal symbols areignored. RX Adaptation module 222 deletes the null or illegal 10-bitsymbols, and uses the deletion frequency to control the RX symbol clockphase locked loop. Thus, the RX symbol clock is phase locked to the TXsymbol clock. Elasticity FIFO 224 compensates for ppm differencesbetween the two PHY clocks. The resulting 10-bit symbol is pushed intoFIFO 116, where conventional 1394b deletable symbols functionalityprevents bport FIFO underflow and overflow. In an embodiment FIFO 116 issized slightly larger than FIFO 110 to compensate for the“4inarushthenawait” symbol arrival characteristics. The remaining bitsfrom register 210 are then stored in register 208, and the next 8-bitbyte received is stored in register 210. Assembly of 10-bit symbolscontinues by using all of the bits from register 208, and appending anybits needed from register 210 to form the 10-bit symbol. This 10-bitsymbol process continues until register 210 is emptied upon appendingbits, at which point the process repeats itself by storing an 8-bit bytein both registers 208, 210 again.

The relationship between 10-bit symbols and 8-bit characters can beconceptualized as illustrated in FIG. 4. In an embodiment, port 114 caninclude four 10-bit registers on the 1394 side of port 114 (referencenumeral 250), and five 8-bit registers on the GMII side of port 114(reference numeral 252), as illustrated in FIG. 5. In an embodiment,symbol transmission begins with transmission of an illegal symbol tosynchronize four 10-bit registers on the 1394b side of port 114 with thefive 8-bit registers on the GMII side of port 114. In this manner, a10-bit symbol transmitted immediately after an illegal symbol isreceived as a valid 10-bit symbol. A clock domain crossing transmit FIFObridges the 1394b PHY clock (running at 98 MHz, in an embodiment) andthe 1000 base clock domains. When the clock domain crossing FIFO drainsbelow a predetermined threshold such that it will underflow after thenext five symbols are transmitted, an illegal symbol is fed into theclock domain crossing FIFO.

In an embodiment of the present invention, training and operationsymbols are transmitted to support scrambler synchronization and a portsynchronization handshake and can utilize K28.5 substitution. Ratherthan GHz logic, or phase locked loops, the present invention utilizessingle clock synchronous logic in the receiver on PHY 106. Bytes arepresented to port 114 from GMII interface 104 synchronously to GMIIinterface 104's RX clock (running at 125 MHz, in an embodiment), and,unlike conventional 1394b ports, there is no requirement for anyhigh-speed bit receive logic or clock recovery in port 114. The K28.5symbol in the IBM 8B10B code is a symbol used in normal operation thatcontains a special “comma” pattern sequence, denoted as 0011111 or110000, depending on disparity. When a receiver initializes upon startup, it is unaware of where the 10-bit boundaries occur in an incomingbit stream. But when it recognizes a received K28.5 symbol (the commasequence), it can use this symbol to determine the 10-bit boundary, andthus acquire symbol synchronization. 1394b-compliant devices performsymbol synchronization by performing K28.5 substitution, replacing D28.0symbols with K28.5 symbols. The receiver uses the K28.5 symbol toacquire symbol synchronization, and also substitutes back the D28.0symbol for any K28.5 symbols it finds in the stream. 1394b-compliantdevices send a training symbol request as the first symbol on a port.This training symbol is scrambled, and the resulting 8B10B data symbolis transmitted. Scrambling the training symbol ensures that periodicallythe received data symbol is a D28.0 symbol, and the K28.5 substitutioncan be performed.

When port 114 has acquired symbol and scrambler synchronization, itchanges the symbol it is transmitting to an operation symbol. Thisoperation symbol conveys another request, and is scrambled onto 8B10Bdata symbols in just the same way. As a result of scrambling, a D28.0symbol is still due to be transmitted occasionally, and K28.5substitution is performed.

When port 114 is both transmitting and receiving operation requestsymbols, it is synchronized to its peer node, and also made aware thatthe peer node is synchronized to port 114. Port training is nowconsidered complete, and port 114 is ready to transmit requests, controlsymbols, and data in its support of the 1394 protocols. The 5-to-4relationship between states on the 1394b side and states on the GMIIside of port 114 can be illustrated in FIG. 5. In an embodiment, port114 utilizes five 8-bit registers (as seen on the GMII side of port 114)a, b, c, d and e, which correspond to four 10-bit registers on the 1394bside of port 114. On the GMII side of port 114, each successive 8-bitcharacter is pushed into register a, b, c, d or e using a value readfrom modulo 5 counter 206 at intervals denoted by the RX clock on GMIIinterface 104. On the 1394b side of port 114, 10-bit data is pulled fromthe GMII side of port 114 using a clock that runs at ⅘ of the GMII RXclock frequency (100 MHz in an embodiment). This clock increments modulo5 counter 206 for each symbol read. The successive values read area[7:0]∥b[7:6], b[5:0]∥c[7:4], c[3:0]∥d[7:2] and finally d[1:0] ∥e[7:0].

Clocking appears as shown in Table 1.

TABLE 1 GMII clock |  |  |  |  |  |  | write   a  b  c  d  e  a  b 100MHz clock  |   |   |   |   |   | phase offset needed < 1394bclock  |   |   |   |   |   | read       ab   bc   cd   de    ab

In an embodiment, illegal symbols are transmitted after the 0 modulo 5symbols have been transmitted since the last illegal symbol wastransmitted, and are also used to synchronize the four 10-bit registerson the 1394b side with the five 8-bit registers on the GMII side. Readand write clock pulses are aligned with the necessary phase offset forthe first symbol received after a synchronizing symbol, and the read andwrite selectors reset to point to register “a” for write and register“ab” for read. The first 10-bit symbol is read one read clock pulselater, after values have been written to both registers a and b. Whilethe four 10-bit registers and five 8-bit registers are synchronizingwith each other, no symbols are read out, nor are any 10-bit symbolspushed into the bport RX FIFO using the 100 MHz clock.

The present invention implements the 8-bit GMII interface 104 as aserial interface, by shifting a byte into the 10-bit register on the1394b side using serial interface FIFO 200. Whenever an illegal symbolis shifted into 10-bit register, it is deleted from FIFO 200. Theillegal symbol can be inserted into any stream, and deleted at the otherend, even without byte/symbol synchronization.

Directing attention to FIG. 6, in another embodiment, the presentinvention can be implemented without RX symbol clock recovery. In thisembodiment, the RX clock on PHY 102 is locked to the TX clock on PHY102. 10-bit symbols are placed in FIFO 200 using flagged encoding. TXadaptation module 220 extracts the 10-bit symbols from FIFO 200 andplaces them in registers 202, 204. In this embodiment, 802.3-compliantidle bytes are used rather than inserting 10-bit null or illegalsymbols. If there is no-symbol available in FIFO 200, then TX Adaptationmodule 220 de-asserts a transmit enabled state (TX_EN) on GMII interface104 for 11 clock periods, which causes PHY 102 to insert 802.3-compliantidle bytes. This embodiment thus meets a requirement in the 802.3standard to periodically insert idle bytes. If there is no symbol inFIFO 200 then TX-EN is de-asserted on PHY 102 for 11 clock periods,which causes PHY 102 to insert the idle bytes. In this embodiment, FIFO200 is appropriately sized to buffer nine 10-bit symbols that accumulateduring the 11 clock periods. On the receive side, RX Adaptation module222 only takes data from GMII interface 104 when receive data valid(RX_DV) is asserted, which is not asserted when 802.3-compliant idlebytes are being received. Using flagged decoding, 10-bit decoded symbolsare pushed into the receive FIFO when available when available. Usually,this occurs on four out of every five clock cycles, but with bursts of11 clocks with no push when RX_DV is de-asserted. In an embodiment,elasticity FIFO 224 handles both the ppm differences between PHY 106 andPHY 102, as well as the frequency difference between the 802.3 bit rateand the 1394 S800 bit rate. Elasticity FIFO 224 thus must be at leastnine symbols deeper than used in 1394b implementations to compensate forthe bursty nature of reception. However, in this embodiment, there is noneed for PHY 102 to recover the TX symbol clock.

Directing attention to FIG. 7, in yet another embodiment, robustencoding is realized, which implements TX adaptation phase knowledge.PHY 102 ensures that the GMII RX clock is locked to the GMII TX clock.Robust encoding module 230 takes a 10-bit symbol from FIFO 200 on fourout of every five GMII TX clocks, and uses TX Adaptation module 220 todetermine the encoding to be used, thus generating a 10-bit encodedsymbol. TX Adaptation module 220 places the extracted symbol intoregisters 202, 204 to generate on every GMII TX clock an 8-bit byte asdescribed above. If there is no symbol available in FIFO 200, thenrobust encoding module 230 instructs TX Adaptation module 220accordingly. TX Adaptation module 220 de-asserts TX_EN on GMII interface104 for 11 clock periods, which causes PHY 102 to insert 802.3-compliantidle bytes. FIFO 200 is appropriately dimensioned to buffer ninesymbols.

The receive side in this embodiment is similar to the receive sideillustrated in FIG. 6 and explained above, with the addition of robustdecoding module 232. Robust decoding module 232 decodes the 10-bitsymbols that result from RX Adaptation module 222's conversion to10-bit, encoded symbols from 8-bit, encoded bytes received from PHY 102.

While numerous methods and apparatus for transmitting 1394-compliantsymbols using a gigabit Ethernet PHY have been illustrated and describedin detail, it is to be understood that many modifications may be made toembodiments of the present invention without departing from the spiritthereof.

1.-28. (canceled)
 29. An apparatus comprising: a first interfaceoperating according to a first protocol; at least one second interface,said at least one second interface adapted to operate according to asecond protocol; a translation apparatus in signal communication withboth said first and at least one second interfaces, said translationapparatus adapted to translate between said first and second protocols;a bridging apparatus adapted to provide logical network addressing fordevices connected to said first interface and said at least one secondinterface; and apparatus enabling, responsive to a negotiation, saidtranslation apparatus or said bridging apparatus.
 30. The apparatus ofclaim 29, wherein said second protocol comprises a high-speed serializedbus protocol.
 31. The apparatus of claim 30, wherein said high-speedserialized bus protocol comprises a Universal Serial Bus (USB) protocol.32. The apparatus of claim 29, wherein at least a portion of said secondinterface carries 8B10B encoded data during operation.
 33. The apparatusof claim 29, wherein said bridging apparatus is configured to: receivean 8B10B symbol at said second interface; decode said 8B10B symbol toproduce a decoded symbol; generate at least one packet based at least inpart on said decoded symbol; and route said at least one packet via anetworking protocol layer.
 34. The apparatus of claim 29, wherein saidnegotiation comprises an autonegotiation sequence that requires no userintervention to complete.
 35. The apparatus of claim 29, wherein: saidfirst interface operates within a first clock domain; said at least onesecond interface operates within a second clock domain; and saidtranslating apparatus is adapted to compensate for differences betweensaid first and second clock domains.
 36. The apparatus of claim 29,wherein said bridging apparatus additionally comprises: link layerapparatus, said link layer apparatus adapted to decode 8B10B symbolsinto packets, and encode packets as 8B10B symbols; and protocol layerapparatus, said protocol layer apparatus adapted to route packets viasaid logical network; wherein said at least one second interface iscapable of data communication with said protocol layer apparatus viasaid link layer apparatus.
 37. The apparatus of claim 29, wherein saidat least one second interface is adapted to detect at least one nullsymbol, said null symbol being used to at least in part determine symbolsynchronization.
 38. The apparatus of claim 37, wherein said at leastone second interface is additionally adapted to receive 8B10B symbols,and said at least one null symbol comprises a K28.5 comma sequence. 39.The apparatus of claim 29, wherein said translation apparatus is furtheradapted to insert or delete one or more control symbols conforming to atleast one of said first and second protocols.
 40. The apparatus of claim29, wherein said bridging apparatus comprises at least a first protocolstack adapted to transmit or receive data encoded according to saidfirst protocol, and a second protocol stack adapted to transmit orreceive data encoded according to said second protocol, saidtransmission or reception by each of said first and second protocolstacks being performed according to a common networking protocol. 41.The apparatus of claim 29, wherein said common networking protocolcomprises the Internet Protocol (IP).
 42. An apparatus comprising: afirst interface adapted to operate according to a first data protocol; asecond interface, said second interface adapted to operate according toa second data protocol that is different than said first data protocol;a translation apparatus in data communication with both said first andsecond interfaces, said translation apparatus adapted to translatebetween said first and second data protocols; a bridging apparatusadapted to provide logical network addressing for a first apparatus indata communication with said first interface and a second apparatus indata communication with said second interface; and routing apparatusconfigured to, responsive to a negotiation sequence, route data via saidtranslation apparatus or said bridging apparatus.
 43. The apparatus ofclaim 42, wherein said second data protocol comprises a high-speedserialized bus protocol.
 44. The apparatus of claim 43, wherein saidhigh-speed serialized bus protocol comprises a Universal Serial Bus(USB) protocol.
 45. The apparatus of claim 42, wherein at least aportion of said second interface carries 8B10B encoded data duringoperation.
 46. The apparatus of claim 42, wherein said bridgingapparatus is configured to: receive an 8B10B symbol at said secondinterface; decode said 8B10B symbol to produce a decoded symbol;generate at least one packet based at least in part on said decodedsymbol; and route said at least one packet via a networking protocollayer.
 47. The apparatus of claim 42, wherein said negotiation comprisesan autonegotiation sequence that requires no user intervention tocomplete.
 48. The apparatus of claim 42, wherein: said first interfaceoperates within a first clock domain; said second interface operateswithin a second clock domain; and said translating apparatus is adaptedto compensate for differences between said first and second clockdomains.
 49. The apparatus of claim 42, wherein said bridging apparatusadditionally comprises: link layer apparatus, said link layer apparatusadapted to decode 8B10B symbols into packets, and encode packets as8B10B symbols; and protocol layer apparatus, said protocol layerapparatus adapted to route packets via said logical network; whereinsaid at least one second interface is capable of data communication withsaid protocol layer apparatus via said link layer apparatus.
 50. Theapparatus of claim 42, wherein said second interface is adapted todetect at least one null symbol, said null symbol being used to at leastin part determine symbol synchronization.
 51. The apparatus of claim 50,wherein said second interface is additionally adapted to receive 8B10Bsymbols, and said at least one null symbol comprises a K28.5 commasequence.
 52. The apparatus of claim 42, wherein said translationapparatus is further adapted to insert or delete one or more controlsymbols conforming to at least one of said first and second dataprotocols.
 53. The apparatus of claim 42, wherein said bridgingapparatus comprises at least a first protocol stack adapted to transmitor receive data encoded according to said first data protocol, and asecond protocol stack adapted to transmit or receive data encodedaccording to said second data protocol, said transmission or receptionby each of said first and second protocol stacks being performedaccording to a common networking protocol.
 54. The apparatus of claim42, wherein said difference in said first and second data protocolscomprises at least a difference in the respective structures of the databeing carried via said protocols.
 55. The apparatus of claim 42, whereinsaid difference in said first and second data protocols comprises atleast a difference in the respective speeds with which the data iscarried via said protocols.
 56. The apparatus of claim 42, wherein saida first interface, second interface, translation apparatus, and routingapparatus are all contained within a single integrated circuit.
 57. Theapparatus of claim 42, wherein said second interface is adapted tooperate according to a plurality of protocols, said plurality ofprotocols comprising at least said second protocol and a third protocolhaving at least one different speed capability than said secondprotocol.
 58. The apparatus of claim 42, further comprising anarbitration apparatus in data communication with said second interfaceand said translation apparatus, said arbitration apparatus adapted toprovide arbitrated, unidirectional data flow between said secondinterface and said first interface via at least said translationapparatus when said routing apparatus routes said data via saidtranslation apparatus.
 59. A method for providing data communicationbetween electronic devices, said method comprising: providing first andsecond interfaces, said first interface being associated with a firstprotocol, said second of said interface being associated with a secondprotocol, and said second interface being adapted to operate withmultiple different protocols including said second protocol; performinga negotiation process; and responsive to said negotiation process,either: translating data sent from said first interface to said secondinterface from said first protocol to said second protocol, ortranslating data sent from said second interface to said first interfacefrom said second protocol to said first protocol; or establishing datacommunication between said first and second interface via a bridgeapparatus, said bridge apparatus providing network addressingcapabilities for said first and second devices.
 60. The method of claim59, wherein said act of establishing communication additionallycomprises the steps of: receiving an 8B10B symbol at said secondinterface; decoding said 8B10B symbol; generating at least one packet;and routing said at least one packet via a networking protocol layer.61. The method of claim 59, wherein said act of translating additionallycomprises arbitrating serial accesses from said first interface to saidsecond interface.
 62. The method of claim 59, wherein said establishingcommunication via a bridge apparatus additionally comprises managing afirst subnet and a second subnet, said first and second subnets coupledto said first and second interfaces, respectively.
 63. The method ofclaim 59, wherein said act of translating provides arbitrated,substantially unidirectional data flow.
 64. The method of claim 59,wherein said act of establishing a logical network providessubstantially simultaneous, bidirectional data flow.
 65. The method ofclaim 59, wherein said negotiation process comprises an autonegotiationsequence that occurs without any manual configuration from a user. 66.The method of claim 59, further comprising determining, using at leastsaid second interface, which of said multiple different protocols shouldbe used by said second interface.
 67. The method of claim 59, whereinsaid translating comprises: translating data rendered in said first orsecond protocol to a third protocol; and subsequently translating saiddata rendered in said third protocol to said second or first protocol,respectively.
 68. The method of claim 59, wherein said third protocolcomprises a high-speed serialized bus protocol.
 69. The method of claim59, wherein said bridge apparatus comprises at least a first protocolstack adapted to transmit or receive data encoded according to saidfirst data protocol, and a second protocol stack adapted to transmit orreceive data encoded according to said second data protocol, saidtransmission or reception by each of said first and second protocolstacks being performed according to a common networking protocol.
 70. Anapparatus comprising: a first interface adapted to operate according toa first data protocol; a second interface, said second interface adaptedto operate according to a second data protocol that is different thansaid first data protocol; arbitration apparatus in data communicationwith both said first and second interfaces, said arbitration apparatusadapted to arbitrate transmit and receive operations so as to provideunidirectional data flow between said first interface and said secondinterface; a bridge apparatus adapted to provide network addressing fora first apparatus in data communication with said first interface and asecond apparatus in data communication with said second interface; androuting apparatus configured to, responsive to a negotiation sequence,route data via said arbitration apparatus or said bridge apparatus. 71.The apparatus of claim 70, wherein said second data protocol comprises ahigh-speed serialized bus protocol.
 72. The apparatus of claim 71,wherein said high-speed serialized bus protocol comprises a UniversalSerial Bus (USB) protocol.
 73. The apparatus of claim 70, wherein atleast a portion of said second interface carries 8B10B encoded dataduring operation.
 74. The apparatus of claim 70, wherein said bridgeapparatus is configured to: receive an 8B10B symbol at said secondinterface; decode said 8B10B symbol to produce a decoded symbol;generate at least one packet based at least in part on said decodedsymbol; and route said at least one packet via a networking protocollayer.
 75. The apparatus of claim 70, wherein said negotiation comprisesan autonegotiation sequence that requires no user intervention tocomplete.
 76. The apparatus of claim 70, further comprising atranslating apparatus in data communication with said first and secondinterfaces, and wherein: said first interface operates within a firstclock domain; said second interface operates within a second clockdomain; and said translating apparatus is adapted to compensate fordifferences between said first and second clock domains.
 77. Theapparatus of claim 70, wherein said bridge apparatus additionallycomprises: link layer apparatus, said link layer apparatus adapted todecode 8B10B symbols into packets, and encode packets as 8B10B symbols;and protocol layer apparatus, said protocol layer apparatus adapted toroute packets via said network; wherein said at least one secondinterface is capable of data communication with said protocol layerapparatus via said link layer apparatus.
 78. The apparatus of claim 70,wherein said second interface is adapted to detect at least one nullsymbol, said null symbol being used to at least in part determine symbolsynchronization.
 79. The apparatus of claim 78, wherein said secondinterface is additionally adapted to receive 8B10B symbols, and said atleast one null symbol comprises a K28.5 comma sequence.
 80. Theapparatus of claim 70, further comprising a translation apparatusadapted to insert or delete one or more control symbols conforming to atleast one of said first and second data protocols.
 81. The apparatus ofclaim 70, wherein said bridge apparatus comprises at least a firstprotocol stack adapted to transmit or receive data encoded according tosaid first data protocol, and a second protocol stack adapted totransmit or receive data encoded according to said second data protocol,said transmission or reception by each of said first and second protocolstacks being performed according to a common networking protocol. 82.The apparatus of claim 70, wherein said difference in said first andsecond data protocols comprises at least a difference in the respectivestructures of the data being carried via said protocols.
 83. Theapparatus of claim 70, wherein said difference in said first and seconddata protocols comprises at least a difference in the respective speedswith which the data is carried via said protocols.
 84. The apparatus ofclaim 70, wherein said a first interface, second interface, arbitrationapparatus, and routing apparatus are all contained within a singleintegrated circuit.
 85. The apparatus of claim 70, wherein said secondinterface is adapted to operate according to a plurality of protocols,said plurality of protocols comprising at least said second protocol anda third protocol having at least one different speed capability thansaid second protocol.
 86. A method of communicating data between a firstdata interface adapted to operate according to a first data protocol anda second data interface adapted to operate according to a second dataprotocol that is different than said first data protocol; negotiatingwhether data should be routed over a first path or a second path, saidfirst path comprising apparatus for arbitration of transmit and receiveoperations so as to provide unidirectional data flow selectively betweensaid first interface and said second interface, said second pathcomprising a bridge apparatus adapted to provide networking for a firstapparatus in data communication with said first interface, and a secondapparatus in data communication with said second interface; andresponsive to said negotiating, routing said data via said first path orsaid second path.
 87. The method of claim 86, further comprisingtranslating between said first and second data protocols when said datais routed over said first path.
 88. The method of claim 87, wherein saidtranslating between said first and second data protocols compriseschanging at least one data structure between said first and secondprotocols.
 89. The method of claim 87, wherein said translating betweensaid first and second data protocols comprises changing at least onedata speed between said first and second protocols.
 90. The method ofclaim 86, wherein said second protocol comprises a high-speed serializedprotocol.
 91. The method of claim 86, wherein said routing said dataover said bridge apparatus further comprises: receiving data encodedaccording to said first data protocol; assembling said data into aplurality of packets via at least one first protocol layer; transmittingsaid packets to at least one second protocol layer; assembling aplurality of symbols from said received packets; and transmitting saidreceived packets to said second first interface.
 92. A method forproviding data communication between at least first and second datainterfaces operating according to first and second data protocols,respectively, said method comprising: performing a negotiation processto select between said first and third protocols; and based at least inpart on a result of said negotiation process, either: (i) translatingbetween said first protocol and said second protocol; or (ii)establishing a logical network utilizing a third protocol, said logicalnetwork providing network addressing capabilities for said at least twodevices, said logical network being established by at least: receivingan 8B10B symbol at said second interface; decoding said 8B10B symbol toproduce a decoded symbol; generating at least one packet based at leastin part on said decoded symbol; and routing said at least one packet viaa networking protocol layer.